6510/65816 Addressing mode: Stack (Software Interrupts) -- s
(BRK,COP)
(2 bytes) (7 and 8 cycles)
+---------------+------------------+-----------------------+----------+
| Cycle | Address Bus | Data Bus |Read/Write|
+---------------+------------------+-----------------------+----------+
| 1 | PBR,PC | Op Code | R |
| (3) 2 | PBR,PC+1 | Signature | R |
| (7) 3 | 0,S | Program Bank Register | W |
| 4 | 0,S-1 | Program Counter High | W |
| 5 | 0,S-2 | Program Counter Low | W |
| 6 | 0,S-3 | (COP Latches)P | W |
| 7 | 0,VA | Abs.Addr. Vector Low | R |
| 8 | 0,VA+1 | Abs.Addr. Vector High | R |
| 1 | 0,AAV | New Op Code | R |
+---------------+------------------+-----------------------+----------+
(3) Special case for aborting instruction. This is the last cycle which
may be aborted or the Status, PBR or DBR registers will be updated.
(7) Subtract 1 cycle for 6502 emulation mode (E=1).
See also: Abbreviations